PangeaOS
ARCH SPEC v1.2.3 •
Normative Specification

PangeaOS Architecture Specification v1.2.3

Ring-0 / Single Address Space Operating System (SASOS) — Fault Containment, Availability, and Hardware Profile Revision (Complete Normative Baseline §0–§12)

0. Priority Revision & Immutable Architectural Conditions

The highest-priority requirement of PangeaOS v1.2.3 is that localized anomalies must never halt the entire operating system, while simultaneously refusing to continue execution if kernel integrity or memory isolation is lost. To achieve both, faults are classified by origin, blast radius, and recoverability: localized faults are quarantined at the domain or device boundary, and only the loss of a trusted boundary is treated as a system-fatal fault. Version 1.2.3 further finalizes the exact virtual address layout, MMU/PKU register profiles, and Two-Stack IST pivot ABIs required for error-free implementation.

0.1 Immutable Architectural Conditions [N]

  1. Universal CPL=0 (Ring-0) Execution: All OS code, device drivers, internal kernel tasks, and domains execute at CPL=0 (Ring-0). Transitions to CPL=3 must not be assumed or introduced.
  2. Pure Single Address Space Operating System (SASOS): All domains share a single virtual address space and a common page-table root (CR3). Per-domain CR3 switching for task context switches or separate per-process address spaces must not be introduced.
  3. Defense-in-Depth Data Isolation: Domain data isolation is realized by combining hardware PKU/PKS on supported CPUs, verified Software Fault Isolation (SFI), authenticated gates (gate-asm), CFI, a generational Capability table, a Page Frame Number (PFN) database (pangea-pfndb), and forced scheduler preemption.
  4. Prohibition of Unverified Code: Dynamic code generation, JIT compilation, execution of unverified code, and arbitrary privileged instruction execution by domains are strictly forbidden.
  5. Gate-Mediated State Updates: CR0.WP=1 is permanently maintained. Updates to page tables, PKRU/PKRS, IOMMU structures, and interrupt control must pass through audited, dedicated single-entry gates.
  6. Rejection of Self-Reported Domain State: Fault handling decisions must never rely on domain-writable stacks, flags, arguments, or self-reported values inside exception frames. Domain IDs, execution states, recovery continuations (SchedulerContinuation), and generation numbers must be read exclusively from Domain 0's protected K0 Per-CPU state.
  7. Honest Scope of Ring-0 Isolation: PangeaOS does not claim that hardware mechanisms alone can isolate arbitrary malicious native Ring-0 code. Localized fault containment targets input attacks, bugs, runaway loops, and forbidden instruction detection within verified code; any event where code bypasses the SFI verifier is treated as a TCB integrity breach (F1).

0.2 Normative Labels

Label Normative Meaning
[N] Normative Requirement: Mandatory requirement. Any build, boot sequence, or release violating this condition is rejected.
[T] Performance / Latency Target: Engineering target to be measured and recorded on hardware, not a security guarantee.
[H] Hardware Verification Item: Behavior that must be confirmed on physical CPUs, microcode revisions, chipsets, and UEFI firmware.
[R] Residual Risk: Threat vector that cannot be completely eliminated under the current architectural design.

"MUST / MUST NOT / SHOULD" are interpreted as normative requirements.

1. Threat Model & Trusted Computing Base (TCB)

1.1 Protected Assets

  • Domain 0 code, the Capability ledger, CSPRNG state, the Page-Table Update Gate, scheduler state, and trusted K0 Per-CPU state.
  • Private data, heaps, and stacks of other domains (Domains 1–12).
  • The PFN database (pangea-pfndb), IOMMU page tables, and interrupt routing configurations.
  • The kernel image, gate code (gate-asm), and build/signature manifests.
  • Overall system availability and fault audit logs.

1.2 In-Scope Adversaries

  • Attackers supplying malicious inputs to induce parse errors, CPU exceptions, infinite loops, excessive allocations, or queue saturation.
  • Attackers exploiting a buggy domain to access memory outside that domain's authorized bounds.
  • Attackers exploiting out-of-range IPC indices, forged Capabilities, stale-generation handles, or double-fetch (TOCTOU) races.
  • Attackers leveraging malicious PCIe DMA, MSI/MSI-X injection, ATS, peer-to-peer (P2P) traffic, or device interrupt storms.
  • Attackers attempting cache or speculative execution side-channel attacks.
  • Supply-chain adversaries targeting dependency crates, compilers, linkers, or the build environment.

1.3 Out-of-Scope Threats (Not Guaranteed by This Specification) [R]

  • Complete compromise of platform firmware or management engines (SMM, Intel ME, AMD PSP).
  • Physical power or electromagnetic (EM) side channels and invasive silicon probing.
  • Universal prevention of hardware DRAM disturbance errors such as Rowhammer across all platforms.
  • Unknown silicon or microcode defects in the CPU.
  • Complete containment of a Ring-0 domain capable of executing arbitrary, unverified malicious instruction sequences.

The final item is paramount: to preserve the Ring-0/SASOS architecture, native domain code must pass SFI and instruction-restriction verification before loading. PangeaOS never claims that MPK alone, Rust types alone, or raw byte-pattern searches alone can isolate arbitrary Ring-0 code.

1.4 Trusted Computing Base (TCB)

The TCB comprises the bootloader and signature verifier, Domain 0, exception and interrupt entries (pangea-irq), gate-asm, the SFI code verifier (domain-verify), bincheck-core, the Page-Table Update Gate, IOMMU HAL, the compiler/LLVM/linker toolchain, CPU/microcode, and firmware. Any addition to the TCB requires formal review, and unauthorized unsafe code (omitted from unsafe-allow.toml) must never be included in a release.

2. Fault Model: Localized Faults vs. System-Fatal Faults

2.1 Core Principle [N]

The occurrence of an anomaly is not a sufficient condition for halting the entire system. Full-system fail-stop is restricted to confirmed loss of a trusted boundary or inability to maintain safe global operation. Invalid inputs, domain panics, timeouts, resource exhaustion, and anomalous device responses are handled via request rejection, domain quarantine, or device isolation.

2.2 Fault Classes

Class Examples Mandatory Processing Full OS Halt
L0: Request Anomaly Invalid length, out-of-range index, unknown opcode, malformed protocol Reject request; increment caller strike count; rate-limit logging. No
L1: Domain-Local Fault Domain d panic!, local #PF/#GP/#UD/#CP, stack canary corruption, verified SFI bounds rejection Halt domain via trusted entry, close permissions, reclaim executing CPUs, and quarantine domain. No (in principle)
L2: Resource Exhaustion / DoS Domain CPU budget or memory quota overrun, IPC queue saturation, log flood Preempt on first CPU overrun, quarantine on repeat; reject memory/queue requests or apply backpressure. No
L3: Subsystem Fault Unresponsive device, IOMMU fault storm, repeated domain restart failure, specific queue corruption Isolate offending device/domain/subsystem; transition to Restricted Mode. No (in principle)
F1: Kernel TCB Integrity Loss Domain 0 invariant corruption, gate-asm hash mismatch, unknown protection state origin, suspected PT tampering Request all-core halt; record minimal emergency log only if safe, and execute Fail-Stop. Yes
F2: Unrecoverable CPU / Memory Fault Uncorrected MCA compromising shared state integrity, loss of trusted exception entry, all-CPU hard lockup Isolate CPU if hardware MCA severity permits; otherwise Fail-Stop. Yes (if integrity lost)
F3: Uncertain Protection State Incomplete TLB shootdown leaving protection changes unconfirmed, or unconfirmed IOMMU invalidation with possible ongoing DMA Never reuse affected frames; isolate CPU/device; Fail-Stop if safe containment cannot be proven. Conditional

2.3 Strict Conditions for System-Fatal Faults [N]

A fault is judged system-fatal if and only if at least one of the following conditions is confirmed from trusted, protected state:

  1. Integrity of Domain 0 code, the Page-Table Update Gate, exception entries, PFN DB, or the Capability ledger cannot be verified.
  2. The executing domain cannot be reliably correlated with the fault context, making it impossible to determine which protection domain to close.
  3. Page-table or PKRU/PKRS protection state is corrupted such that access to other domains' secrets cannot be reliably denied.
  4. Cessation of DMA cannot be confirmed, continued access to sensitive memory is suspected, and no alternative means exists to isolate the device.
  5. The trusted stack for synchronous or exception handling is itself corrupted, preventing safe execution of localized recovery code.
  6. An uncorrected CPU Machine Check (#MC) or equivalent platform fault indicates that shared memory reliability has been lost.

The system MUST NOT halt solely due to: a domain panic, a general protection fault inside a single domain, service response latency, malformed external requests, IPC capacity violations, an interrupt storm from a single device, quota overruns, or a domain exceeding its restart limit.

2.4 Fault Attribution & Uncertainty

  • Active Domain ID, domain generation, CPU ID, execution budget, and recovery continuation are read from Domain 0's K0 Per-CPU region.
  • Exception frame values are inspected structurally as CPU-saved register state, but self-reported values copied onto a domain's writable stack are never trusted.
  • When attribution is uncertain, the kernel first isolates the affected CPU or domain; uncertain attribution does not immediately equate to full-OS halt, unless impact on the TCB boundary cannot be ruled out (F1/F3).
  • Runtime SFI bounds-check rejections are handled as L1, whereas suspected bypass of the SFI verifier itself (or unauthorized WRPKRU execution) is treated as F1.
  • Fault recurrence counts are tracked using generational counters protected in Domain 0 (K0).

3. Ring-0 SASOS Domains, Virtual Address Layout & Code Verification

3.1 Shared Address Space & 48-Bit Canonical Virtual Memory Map [N]

All CPUs share an identical virtual address layout and page-table root (CR3). Per-domain CR3 switching on task transitions is forbidden. In v1.2.3, to enable $O(1)$ bitwise SFI bounds verification and eliminate permanent direct mapping of all physical RAM, the 48-bit canonical virtual address layout is finalized as follows:

Virtual Address Range Size / PML4 Index Designated Purpose & Owner Protection Key PTE Attributes (U/S, W, NX)
0x0000_0000_0000_0000 .. 0x0000_0000_001F_FFFF 2 MB (PML4[0] head) Virtual NULL Guard — P=0, NX=1 (Unmapped)
0x0000_0100_0000_0000 .. 0x0000_0CFF_FFFF_FFFF 12 TB (PML4[2..25])
1 TB / Domain		 Domain 1–12 Sandbox Arena
Domain d window: (addr >> 40) == d		 K1–K12 Data/Heap/Stack: W=1, NX=1
Domain Code: U/S=0, W=0, NX=0
0xFFFF_8000_0000_0000 .. 0xFFFF_807F_FFFF_FFFF 512 GB (PML4[256]) Domain 0 Private State & Per-CPU (percpu, cap-core, k0_priv_rsp) K0 W=1, NX=1 (Bracketed by Guard Pages)
0xFFFF_8080_0000_0000 .. 0xFFFF_80FF_FFFF_FFFF 512 GB (PML4[257]) Supervisor IST Bootstrap Stacks (IST 1..4) & GDT/IDT/TSS K0 / Non-key RO IST: U/S=0, W=1, NX=1
GDT/IDT: U/S=0, W=0, NX=1
0xFFFF_8100_0000_0000 .. 0xFFFF_817F_FFFF_FFFF 512 GB (PML4[258]) PFN Database (pangea-pfndb) K0 W=1, NX=1
0xFFFF_8200_0000_0000 .. 0xFFFF_827F_FFFF_FFFF 512 GB (PML4[259]) Page-Table Hierarchy Window (pangea-mmu) K13 W=1, NX=1 (Normally K13 is RO/NA)
0xFFFF_8300_0000_0000 .. 0xFFFF_837F_FFFF_FFFF 512 GB (PML4[260]) IPC Control & Ring Window (pangea-ring) K14 W=1, NX=1 (Domain mask sets K14 to RO)
0xFFFF_8400_0000_0000 .. 0xFFFF_847F_FFFF_FFFF 512 GB (PML4[261]) CMEE Quarantine Erasure Window (cmee) K15 W=1, NX=1 (K15 is NA outside CMEE Gate)
0xFFFF_FFFF_8000_0000 .. 0xFFFF_FFFF_FFFF_FFFF 2 GB (PML4[511] top) Kernel Core .text, .rodata, gate-asm K0 .text/gate-asm: U/S=0, W=0, NX=0
.rodata: U/S=0, W=0, NX=1

3.2 Role of MPK/PKS, Key Allocation & Hardware U/S + SMEP/SMAP Profiles [N] [H]

MPK/PKS is a data-access control layer, not an instruction-execution boundary. Keys are assigned as K0 (Domain 0 private state), K1–K12 (Domains 1–12 private data/heap/stack), K13 (Page-table hierarchy), K14 (IPC control metadata), and K15 (CMEE quarantine erasure region).

Hardware Profile Resolution (Profile P-PKS vs. Profile P-PKU):

  • Profile P-PKS (CR4.PKS=1 capable CPUs): All pages are mapped U/S=0 with CR0.WP=1, CR4.SMEP=1, CR4.SMAP=1, and gate-asm updates IA32_PKRS (0x6E1) with absolute masks.
  • Profile P-PKU (CR4.PKE=1 standard CPUs): Because PKRU applies only to U/S=1 pages while CR4.SMEP=1 faults on CPL=0 instruction fetches from U/S=1 pages, all executable code pages (.text, gate-asm, verified domain code) and Supervisor IST Bootstrap Stacks are mapped U/S=0, whereas all key-protected data pages (K0–K15 data/heap/stack/PT/IPC/CMEE) are mapped U/S=1, NX=1 with CR0.WP=1, CR4.SMEP=1, CR4.SMAP=0. This guarantees 100% hardware enforcement of PKRU data permissions in Ring-0 while doubly preventing execution of data pages via NX=1 and SMEP=1.

Domain code is validated against a positive instruction allowlist. In PKU mode, both WRPKRU and XRSTOR-family instructions are banned from domain code, and the PKRU component (Bit 9) is masked out of XSAVE restoration masks.

3.3 Three-Class SFI Verifier & bincheck [N]

Verification is divided into three classes executed both post-link and post-S-KARL relocation:

  1. Class A (Byte-Sequence & Manifest Rules): Verifies fixed gate blobs, signatures, golden hashes, and absence of embedded data in executable sections.
  2. Class B (Exact Instruction-Boundary Decoding): Decodes executable sections with a full x86-64 decoder against the positive allowlist, rejecting WRPKRU, WRMSR, MOV CRx/DRx, XRSTOR/XRSTORS/XSETBV, SWAPGS, WRFSBASE/WRGSBASE, CLI/STI, flag-altering POPFQ, LGDT/LIDT/LTR, IN/OUT, STAC/CLAC, arbitrary IRETQ/HLT, unauthorized CET shadow-stack ops, and RDPMC.
  3. Class C (Control-Flow & 1TB-Arena Memory Bounds Verification): Proves that all branches, calls, returns, and memory accesses remain within verified CFG targets and the owning domain's 1TB virtual window ((addr >> 40) == d) or target authenticated gates.

3.4 Authenticated Non-Generic Gates [N]

PKRU/PKRS changes, page-table updates, IOMMU updates, interrupt routing changes, and domain teardown execute exclusively through dedicated, non-generic single-entry assembly gates (gate-asm). Gates apply precomputed absolute PKRU constants and verify runtime Capability handles (owner, generation, alignment, and rights) against Domain 0's K0 ledger.

4. Two-Stack Entry Protocol & Localized Panic Recovery

4.1 Two-Stack Entry Protocol (IST Pivot to k0_priv_rsp) [N]

Because CPL0-to-CPL0 exceptions do not switch stacks via TSS.RSP0, PangeaOS assigns dedicated Supervisor IST bootstrap stacks (IST 1: general exceptions/IRQ trampoline, IST 2: #DF, IST 3: NMI, IST 4: #MC, mapped U/S=0, W=1, NX=1 with 4KB Guard Pages and matching CET ISST entries):

  1. On exception/IRQ entry, the CPU switches to IST 1 (U/S=0, immune to PKRU blocking) and pushes the hardware exception frame.
  2. Before touching any K0 memory, the entry stub saves general-purpose registers and the interrupted PKRU on IST 1, then immediately switches PKRU to the absolute bootstrap mask (PKRU_KERNEL_DEFAULT).
  3. With K0 access established, the stub accesses K0 Per-CPU state via GS:, validates the active Domain ID, generation, and reentrancy depth, copies the frame, and immediately pivots RSP onto the kernel private exception stack (k0_priv_rsp in K0), freeing IST 1 against nested exceptions.
  4. The stub executes cld (DF=0), aligns the stack to 16 bytes (and rsp, -16), and invokes the Rust dispatcher.
  5. For localized faults (L1), the kernel revokes domain permissions and performs a non-local jump (gate_abort_to_scheduler) to the K0 Per-CPU SchedulerContinuation, never executing ret onto the damaged domain stack.
  6. Unhandled reentrancy, trusted stack corruption, or continuation mismatch escalates to F1/F2.

4.2 Fault Attribution Table [N]

  • panic!, #PF/#GP/#UD, #CP (CFI violation), CPU budget overrun, NMI watchdog lockup, or IOMMU fault attributable to Domain $d \neq 0$ → Quarantine domain / isolate device (L1/L2/L3).
  • Any fault originating in Domain 0, unattributable context, unisolatable #DF, uncorrected shared-state #MC, or unconfirmed IOMMU protection state → F1/F2/F3 Fail-Stop.

4.3 Panic Policy & CPU Flag Rules [N]

  • Attacker-controlled inputs must be validated with Result, never assert!, unwrap(), or expect().
  • Domain panic! routes to pangea_panic_dispatch_trusted() -> ! (gate_abort_to_scheduler), which switches to the trusted stack and jumps to the scheduler continuation without dynamic allocation or blocking locks.
  • CLI, STI, flag-changing POPFQ, IRETQ, and HLT are banned from domain code; DF=0 is enforced at all domain and exception entries.

5. DoS Resilience, Watchdogs & Resource Quotas

5.1 Forced CPU Time Limits & NMI Watchdog [N]

Each domain has an independent CPU budget enforced by the APIC timer or verified TSC-deadline timer (initial quantum target: 1 ms [T]). The NMI watchdog detects CPUs where maskable interrupts cease progressing and terminates the attributed domain rather than defaulting to an all-core halt (unless NMI/trusted state itself is corrupted: F1/F2).

5.2 Resource Quotas, Backpressure & DoS Suppression [N]

Domain 0 enforces per-domain quotas on CPU time, total pages, heap bytes, DMA pins, IPC ring depth, message rates, interrupt/fault rates, and restart counts. Quota exhaustion returns Err(QuotaExceeded) (L2) without panicking the global allocator. Domain 0 reserves dedicated emergency memory, recovery stacks, and token-bucket rate-limited per-CPU log rings. Domain/device restarts are governed by retry caps, exponential backoff, and a circuit breaker.

6. Scheduler State Machine & Multi-Core Quarantine Procedure

6.1 Execution State Machine [N]

Created → Verified → Ready → Running → Quiescing → Quarantined → (Reinitialize → Verified) or PermanentlyDisabled

6.2 Safe SMP Domain Termination Sequence [N]

  1. Transition domain state to Quiescing in Domain 0's ledger and block new Capability issuance.
  2. Send halt IPIs (with watchdog/NMI fallback) to all cores executing the domain.
  3. Confirm via trusted entry that each core has reset PKRU/PKRS to PKRU_KERNEL_DEFAULT and invalidated the domain continuation.
  4. Do not reuse shared pages, stacks, or shadow stacks until all cores acknowledge.
  5. Disable IOMMU device BME=0 and await IOTLB and Interrupt Remapping invalidation completion.
  6. Revoke capabilities by incrementing the domain generation number.
  7. Quarantine, zeroize (cmee), verify, and release frames; any frame lacking completion ACKs remains pinned.
  8. Evaluate restart rate limits; regenerate from a clean verified image if permitted, or transition to PermanentlyDisabled.

6.3 Intra-Domain Coroutines

Context switching does not claim to be a bare RSP/RBP swap when CET Shadow Stacks are active; PangeaOS adopts stackless Future coroutines with explicit yield points and timer-driven preemption, treating cycle counts strictly as [T] targets.

7. Memory Management, Page-Table Updates & Dual-Class IPC

7.1 Virtual Addresses & PFN Database (pangea-pfndb) [N]

The NULL guard unmaps virtual addresses near 0x0. Permanent direct mapping of all physical memory is prohibited. The PFN DB tracks Free → Allocated(domain, generation) → Quarantine → Erased → Free plus Guard, Reserved, DmaPinned, PageTable, KernelImage, and ShadowStack, catching double-frees, generation mismatches, and freeing of DmaPinned frames at runtime.

7.2 K13 PT Update Gate & TLB Shootdown [N]

Page-table frames reside in K13 (normally write-disabled even for Domain 0). Updates execute exclusively inside the single PT Update Gate while maintaining CR0.WP=1: lock target mappings → update PTE inside gate → issue local INVLPG/INVPCID and cross-core TLB shootdown → await all CPU and IOTLB ACKs (pin frames and isolate under F3 on timeout).

7.3 Pangea Ring I/O — Class S & Class B [N]

Because a single shared SASOS page table cannot simultaneously grant Producer-RW and Consumer-RO permissions on the same page:

  • Class S (Brokered Copy): K14 control indices are Read-Only to domains and updated via the IPC Gate; a verified Domain 0 broker validates bounds and copies data.
  • Class B (Re-Keyed Zero-Copy): Re-keys the data frame's Protection Key and enforces an intermediate inaccessible state across all CPUs until PKRU/PKRS and TLB synchronization complete.
  • Ring Validation Rules: Validate tail.wrapping_sub(head) <= capacity on a single local snapshot of untrusted indices/descriptors (forbidding double-fetch re-reads). Queue full or invalid index conditions are handled as L0/L2, never triggering an OS halt.

7.4 DMA, IOMMU & Software Zeroization (CMEE) Claims [N]

Devices start with BME=0; BME=1 is prohibited until IOVA mapping and IOTLB invalidation complete. Unverified ATS/PRI/PASID are disabled. Device fault storms trigger BME=0, IOTLB/IR invalidation, optional PCIe FLR, and quarantine. CMEE (cmee) is defined strictly as software zeroization and PFN state transition management prior to reuse, distinct from hardware memory encryption (TME/SME) required for physical Cold Boot defense.

8. Boot Handoff, CPU Profiles & Post-Relocation Verification

  • UEFI Handoff [N]: ExitBootServices() retries memory map acquisition with the latest Memory Map Key up to a fixed limit. SMM/ME/PSP remain in the TCB/residual risk [R]. ACPI tables are parsed with strict allowlists, bounds, and checksums (no AML interpreter).
  • Strict CPU Capability Profile [N]: cpu-features verifies SMEP, PKU/PKS, NX, x2APIC, CET, and IOMMU/IR at boot, refusing to boot or fall back to unverified paths if requirements are missing.
  • S-KARL & Post-Relocation Verification [N]: Function shuffling provides layout diversity (not absolute secrecy). bincheck-core re-verifies instruction boundaries, CFG, SFI, gate hashes, and forbidden instructions after relocation (up to 8 bounded retries; boot abort on failure), then scrubs relocation/symbol metadata.

9. Recovery Sequence, Regeneration & Restricted Mode

Quarantined domains follow the 9-step revocation sequence (§9.1), logging only fixed-size structured audit records (never formatting attacker-controlled strings). Clean regeneration (§9.2) requires signature verification and confirmed completion of all DMA/TLB/IOTLB invalidations. When a non-core service or device is permanently disabled, independent domains continue operating in Restricted Mode (§9.3) provided Domain 0 invariants remain intact.

10. Build Gates, Mandatory DoS Regressions & Release Blockers

CI enforces formatting, lints, overflow checks, unsafe-allow.toml, unit/property tests, fuzzing (ACPI/PCI, IPC descriptors, memory map, capabilities), ircheck, instruction-boundary bincheck, SFI/CFG verifiers (both post-link and post-relocation), reproducible builds, QEMU fault injection, and physical hardware tests across all 12 mandatory DoS regression scenarios (§10.2). Any unproved claim of arbitrary Ring-0 isolation or incomplete TLB/IOTLB reclamation blocks release (§10.3).

11. Major Technical Corrections & Finalizations from v1.2 / v1.2.2

Previous Architectural Issue v1.2.2 / v1.2.3 Normative Resolution
Domain panics and general exceptions easily halted the entire OS Standardized L0–L3 localized quarantine vs. F1–F3 fatal conditions.
Interrupt stub relied on domain stack and domain-saved PKRU Finalized Two-Stack Entry Protocol: Supervisor IST (U/S=0) pivot to k0_priv_rsp + K0 Per-CPU saved PKRU and continuations.
PKRU could be restored via XRSTOR Excluded PKRU (Bit 9) from XSAVE restoration masks and banned XRSTOR family in domain code.
Searched all byte offsets for privileged opcodes Separated into Class A (hashes), Class B (exact instruction-boundary decoding), and Class C (CFG/SFI verification).
Potential conflict between Ring-0 PKRU (U/S=1) and CR4.SMEP=1 Finalized Profile P-PKU: all code & IST mapped U/S=0; key-protected data mapped U/S=1, NX=1 with WP=1, SMEP=1, SMAP=0.
SFI memory bounds target addresses were unspecified Assigned fixed 1TB virtual windows per domain (0x0000_0100_0000_0000..0x0000_0CFF_FFFF_FFFF, (addr >> 40) == d).
Assumed per-peer RO/RW permissions on shared SASOS page tables Separated IPC into Class S (brokered copy) and Class B (re-keyed zero-copy with SMP shootdown).
Permanent RO page tables conflicted with runtime updates Placed page tables in K13, writable only inside the single PT Update Gate with TLB shootdown ACK wait.
Claimed MOVNTI guaranteed physical DRAM Cold Boot erasure Defined CMEE as software zeroization prior to reuse; separated hardware TME/SME Cold Boot requirements.

12. Residual Risks & Honesty of Security Claims

  1. This document is a normative design and implementation baseline, not proof of a completed or formally verified kernel.
  2. Guaranteed localized recovery requires verified native code, complete forbidden-instruction enforcement, non-maskable preemption rules, trusted entries, and SMP reclamation protocols working together.
  3. Because Ring-0/SASOS is maintained, any soundness hole in the SFI verifier, gate implementation, or CPU/firmware compromises the TCB.
  4. The NMI watchdog cannot recover from total CPU hardware failure or corrupted NMI pathways.
  5. The engineering objective is to localize all localizable faults, restrict full-system halts strictly to TCB integrity loss, and transition deterministically to Restricted Mode for all other subsystem failures.

References

  • Intel® 64 and IA-32 Architectures Software Developer's Manuals: https://www.intel.com/content/www/us/en/developer/articles/technical/intel-sdm.html
  • UEFI Specification 2.10, Boot Services / ExitBootServices(): https://uefi.org/specs/UEFI/2.10/07_Services_Boot_Services.html
  • The Embedded Rust Book, Panicking: https://doc.rust-lang.org/beta/embedded-book/start/panicking.html
  • Linux kernel documentation, softlockup / hardlockup watchdog concepts: https://cdn.kernel.org/doc/html/latest/admin-guide/lockup-watchdogs.html